1S10 dev. board and MAX Freq.

My experience is that the bad paths tend to be those to and from the hardware multiplier.

The multiplier is also used for shifts and rotates. As an experiment, you can

remove the hardware multiplier and see the effect on your Fmax.

Just hand-edit your system PTF file and change remove_hardware_multipler from "0" to "1"

and then regenerate your system in SOPC Builder. Make sure you aren't running SOPC builder

while you hand-edit the system PTF. You should also recompile your application so that

the compiler won't try to use multiply instructions. Your shift and rotate instructions will take more

cycles now because they don't have the hardware multipler anymore to accelerate them.

Here's another trick to reduce LE usage and sometimes increase Fmax.

It uses a little known setting in Quartus.

Go into the "More Settings" tab of the Fitter options and look for the register packing option.

It defaults to auto. Change it to something like "Minimize with chains".

I'm doing this at home from memory so I might not have the names exact.

What this option does is to make Quartus more aggressive about combining unrelated

registers and lookup-tables into the same LE. They don't turn it on by default because

it tends to use more routing resources. It is very rare for Stratix parts to run out of

routing resources so you should be okay.

BTW, my experiments during development suggested that the Nios II/s and Nios II/f have similar Fmax characteristics.

Sounds like you are finding contrary results. I'd like to know about your configuration if

this is true.