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Altera_Forum's avatar
Altera_Forum
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15 years ago

16 bit avalon tristate slave

Hello

I have a custom h/w for NiosII development using Cyclone III FPGA. I have 512k x 16 bit cypress SRAM. In SOPC builder I created a custom 16 bit Avalon tristate slave for SRAM interface. For some simple data transfer (in application code) it worked fine. But when I tried to put my program into my SRAM, things went wrong. It shows;

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Processor is already paused

Reading System ID at address 0x00412068: verified

Initializing CPU cache (if present)

OK

Downloading 00300000 ( 0%)

Downloading 00408020 (91%)

Downloaded 4KB in 0.0s

Verifying 00300000 ( 0%)

Verify failed between address 0x300000 and 0x300D87

Leaving target processor paused

Is it possibe to download your code into a 16 bit avalon tristate slave???:eek:

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    There could be a couple of reasons here.

    And of course it is possible to mix different bit widths, the avalon switch fabric takes care about it when a master accesses a slave with a different bit width

    1. do you get any timing waring during quartus compilation ?

    2. have you checked your external signals against over and undershot ? undershots can lead to shifting the signal levels in a way that a component "thinks" it is active.

    3. how do you do you timing control, via wait states or did set up the timing for setup access and hold ?

    4. is you external memory attached as a memory or a register, i am asking about the alignment.