16 bit avalon tristate slave

There could be a couple of reasons here.

And of course it is possible to mix different bit widths, the avalon switch fabric takes care about it when a master accesses a slave with a different bit width

1. do you get any timing waring during quartus compilation ?

2. have you checked your external signals against over and undershot ? undershots can lead to shifting the signal levels in a way that a component "thinks" it is active.

3. how do you do you timing control, via wait states or did set up the timing for setup access and hold ?

4. is you external memory attached as a memory or a register, i am asking about the alignment.