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The EPCS SPI block is only available attached to the boot code (I think this is so that the boot code can access it at a known offset from the program counter). So it you want to use the EPCS SPI interface (but not boot from it) you have to waste the memory block.
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If you want to save the memory block, you can build your own EPCS controller slave based on the ALTASMI_PARALLEL function.
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I also did some quick ball-park calculations and think that a 100MHz nios cpu could directly bit-bang the EPCS memory almost as fast as it can be driven by the SPI block. Since the most likely reason for such accesses are writes, the speed of the transfers won't be the limiting factor.Even a factor of 2 or 4 slowdown in a read-verify wouldn't really matter.The direct bit-bang code would also be a lot smaller than the existing nested morass of code of the HAL EPCS functions.
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http://www.alterawiki.com/wiki/epcs_bootloaders has a 380 byte bootloader written in ASM with multiple image support.I doubt it's possible to write an equivalent bit-banged bootloader in much less code.
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