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晓孙0002's avatar
晓孙0002
Icon for New Contributor rankNew Contributor
6 years ago

XXX. Sof was downloaded to FPGA, Contains a 5G LDPC IP,i find the signal (sink_ready) always low,

I dowmload a xxx.sofwhich contains a 5G LDPC IP，I confirm the rst_n​ is high，but the 5G LDPC output signal (sink_ready)and (source_ready) is low, I generated xxx.sof is not xxx_time_limited.sof.
晓孙0002's avatar
晓孙0002
Icon for New Contributor rankNew Contributor
6 years ago

I used the Intel arria 10 GX official development board and wrote a new piece of code at home due to our illness. Attached is my engineering document.

​

I find that many internal signals of LDPC ﹣ 5g IP are optimized.

quartus prime pro 19.1​

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi, Thanks for your update. I have run compilation with your design in Q19.4Pro which was currently available in my local PC. As I checked the RTL viewer, post-mapping and post-fitting, I can see that the important signals ie data, clock, sink_sop/eop are still available. Just wonder if you are seeing the same as following: [cid:image001.jpg@01D5DE84.05929700] By the way, for testing purpose, just wonder if you have had a chance to create simple design with only 5G LDPC IP instance. Then feed dummy fix data and direct clock signal from oscillator. Just to check if after releasing reset, will the sink_ready go high. From the simulation and user guide, with clock and reset correctly, the sink_ready should be able to assert. Thank you. Best regards, Chee Pin