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晓孙0002's avatar
晓孙0002
Icon for New Contributor rankNew Contributor
6 years ago

XXX. Sof was downloaded to FPGA, Contains a 5G LDPC IP,i find the signal (sink_ready) always low,

I dowmload a xxx.sofwhich contains a 5G LDPC IP，I confirm the rst_n​ is high，but the 5G LDPC output signal (sink_ready)and (source_ready) is low, I generated xxx.sof is not xxx_time_limited.sof.
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

As I understand it, you are observing an issue with 5G LDPC IP in hardware where the signaltap seems to be showing sink_ready stuck at 0. To facilitate further debugging, would you mind to try to perform Modelsim simulation with your design to see if you can observe similar issue. If similar issue is observed, you may also cross check with the simulation example generated by the 5G LDPC IP to see if can spot any anomaly.

For your information, I have tested simulating the example design in Modelsim and seems like it is functioning.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

  • 晓孙0002's avatar
    晓孙0002
    Icon for New Contributor rankNew Contributor
    6 years ago

    LDPC IP in my hardware has been verified in Modelsim, and the simulation has been successfully compared with MATLAB. Only when it is verified in FPGA, it is found that the sink ready signal is low. When I added the input and output signals to HDL for verification, I connected them to the pin except for the sink [data]. I found that in post fit, the compiler automatically connected the signals to GND. I confirm that my reset signal is normal. The signals about LDPC are all 0