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Altera_Forum
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19 years ago

Wishful feature for DSP Builder

In most of my design (in RTL), I used the “generate” statement so that the IP can be parameterized under different conditions/parameter ( like “generate if” in Verilog), or fo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

The test of HIL and SignalTAP are completely different model.

It is not so necessary to use the Singaltap in the HIL Because you can just do the partial of the design into HIL project. You don't have to put the whole project into the design.

And also, you can put the signaltap and HIL into the same model and run them seperatedly. Since the HIL is only the simulation, too. It's might not be the very good idea to embed the SignalTap into the HIL.