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Altera_Forum
Honored Contributor
Honored ContributorWishful feature for DSP Builder
In most of my design (in RTL), I used the “generate” statement so that the IP can be parameterized under different conditions/parameter ( like “generate if” in Verilog), or fo...
Altera_ForumHonored Contributor
Honored ContributorI agree with 1.
For 3, it's definitely a problem. I wanted to have a way of using signal tap, scope and display to probe inside the HIL project. Is that what you mean?
