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Altera_Forum
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19 years ago

Wishful feature for DSP Builder

In most of my design (in RTL), I used the “generate” statement so that the IP can be parameterized under different conditions/parameter ( like “generate if” in Verilog), or fo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Hi Wronghorizon,

1. When do the simulation, the output from the HIL block is the HIL simulation result. Other that this, all of the will be the simulink result. It's not too difficult to identify

2. It could be that the HIL test is not the same device as the DSPbuilder project. Thus the customer might lose the chance to configure, if only compile it once.

3. Signal Tap, Scope, and Display are all allowed in the design already.

Butonlyif