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Altera_Forum's avatar
Altera_Forum
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19 years ago

Wishful feature for DSP Builder

In most of my design (in RTL), I used the “generate” statement so that the IP can be parameterized under different conditions/parameter ( like “generate if” in Verilog), or fo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Wish List:

1. Certain status/message to indicate if the current simulation is native Simulink simulation or HIL simulation. There was a case that I had problem with HIL, but hitting the simulink simulation button would still trigger native simulink simulation. I just can’t tell if the undergoing simulations is native or HIL.

2. It would be great if user doesn’t need to compile twice to use HIL. In theory, the tool can be made to compile just once, right? Compiling twice easily offset the benefit of faster simulation time.

3. Allow signal tap or scope/display in the design.