Why use DSP builder over HDL

So, like anything, there are a lot of possible answers to this. In case you weren't aware, DSP Builder has two tools: DSP Builder and DSP Builder Advanced Blockset which changes my opinion some.

Generally, the benefit of Simulink I believe is the simulation environment. Its much faster that modelsim and is much easier to generate vectors, apply them and collect the result. Sweeping parameters for things like fixed point analysis and filter lengths, sample rates, is also easier. This works well for algorithms which are somewhat feedforward with relatively light control. Your not going to replace a DSP with DSP builder, but a upconverter is rather straightforward

DSP Builder (Standard) is a WYSIWYG type flow which you could argue is schematic like, other than the fact it allows you to have some high level models and manage your types. DSP Builder Advanced Blockset is an entirely different beast. This tool does all sort of things you cant do in HDL. Namely, it allows you to describe an algorithm without any FPGA type constructs:

- no pipelining: the data flow is described with no pipelining, just algorithmic latency, the selected device and desired clock rate allows the tool to pipeline and balance the delays to meet your fmax target.

- implementation tradeoffs: for things like memories and multipliers, you can specify a threshold number of logic elements above which the memory or multiplier is implemented in hard blocks, but otherwise can be done in the logic fabric.

- processor bus generation: You can drop down 'source' and 'sink' blocks that will get rolled up into an Avalon MM Slave without any hand coding.

- vector / array support: you can use vectors and do vector math. limited number of blocks now, but you can build your own pretty easy as the tool can work with the math

-complex support: self explanatory. This means you can filter 16 channels of I and Q data against a real filter with effectively 1 block.

-folding/ automated TDMing: this is the coolest one. You do your design completely parallel and specify a sample rate. The tool can look at the FPGA clock rate relative to the specified sample rate and timeshare the memories and multipliers to reduce the size of the design.

(the last 3 items are in the 9.1 release next month I think)

I think the key thing with the advanced blockset is it allows 'portable' IP. Not to another tool obviously, but if you find a small requirements change, change devices or move to a new FPGA family with different resources retargeting takes 5 minutes. Its also nice when you find out at the end of the design you've under or overestimated your potential fmax, so you can 'refold' your design on the fly to reduce the resources if it turns out you could run faster, or lower your fmax and refold without throwing out all your old code as with RTL.

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