Why there's no clock on afi_clk output of the Hard DDR3 Memory Controller, although clock on pll_ref_clk input is present?

I've a problem running DDR3 HMC on Cyclone V SoC Development Board. I instantiated HMC megafunction in schematic top level file, made mem_ pin assignments, connected pll_ref_clk pin to CLK_BOT1 board...