Forum Discussion

New Contributor

7 years ago

Why there's no clock on afi_clk output of the Hard DDR3 Memory Controller, although clock on pll_ref_clk input is present?

I've a problem running DDR3 HMC on Cyclone V SoC Development Board. I instantiated HMC megafunction in schematic top level file, made mem_ pin assignments, connected pll_ref_clk pin to CLK_BOT1 board...

sstrell

Super Contributor

7 years ago

What is your indication that afi_clk is not running?

You can get any interface out of a Platform Designer system by adding in a bridge component and exporting the extra interface. You'd use a clock bridge component for this, but since you are using the hardened interface, I don't know if it's possible to connect that back to soft FPGA logic.

Are you seeing the user clock coming from the IP?

Forum Discussion

Why there's no clock on afi_clk output of the Hard DDR3 Memory Controller, although clock on pll_ref_clk input is present?

Recent Discussions

Agilex 7 slew rate reconfiguration

Agilex-7 AXI MCDMA for PCIe hang

Constraints not being picked for DCFIFO

Can't generate F-Tile Ethernet Hard IP Design Example

MAX10 TSE reference design