Why there's no clock on afi_clk output of the Hard DDR3 Memory Controller, although clock on pll_ref_clk input is present?

Thanks for the reply, NAli1,

I actually did that. Basically I set the same settings in my megafunction as in fpga_sdram Qsys component of the reference design. The differences are only in chip/board timing constrains, in physical chip interface width (reference design uses two DDR3 chips as opposed to mine which uses one), and in Avalone MM interface width. But I can't see how are these differences relevant to the complete absence of UniPHY generated clock (afi_clk). The clock settings are the same as are the pin assignments.

I was going to check the same afi_clk clock in reference design, but run into another trouble using Qsys: i can't export component pin which is also used internally. It's avaliable ether for internal use, or for export.