Honored ContributorI add a on-chip dual clock ram with on-chip memory?
but it has no read signal for two port,why? and how to read the ram with this circumstance? ??write high for write,and low for read? thank!
Honored Contributorimagine that when you write data into sram.
you specify the address, but in some case you don't want write data. therefore you need write_enable signal. how about read sequence? read data appear as you specify address. if you don't want to use the data? just ignore it. that is why you don't need read_enable signal.Honored ContributorAre you generating this onchip memory for NIOS II as
in normal IP generation case i feel it rd_enable will be there but in Nios II situation we use IORD_32direct and read enable will not be available for user to controlHonored Contributorthanks all!
I use this dpram for nios2 and my logic.on port for nios2 and another for my logic. so I want to known how to access the dpram for my logic without read signal. i think akira is right. I will test it !
