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XG_Kang's avatar
XG_Kang
Icon for New Contributor rankNew Contributor
5 years ago
Solved

why pcie_tx_st_ready keep low for almost 16384 pcie_clk

My FPGA design sends continueous MWr TLP packets to CPU module on pcie gen2x4 link。The fpga design use Intel's Arria10 PCIE HIP 。When sending contineous MWr TLP packets，the tx_st_ready signal of th...
  • BoonT_Intel's avatar
    BoonT_Intel
    5 years ago

    Hello Sir,

    Probably this is due to the receiver buffer at the host is out of credit limit. I believe the pull-down is expected if you send continuous back-to-back TLP packets.

    Maybe you can find a way to increase the frequency of sending updateFC (credit update) packet from the receiver side.


BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.