Why don't we simulate the synthesis code ?

Some Altera (and 3rd party) IP cores use encrypted source files. While this encrypted source can be decrypted and synthesised by Quartus, it cannot be read by simulator tools such as ModelSim. To get around this Qsys will generate a separate code base for simulation that will substitute the encrypted RTL code for something that ModelSim can read. This may take the from of some manually written clear-text model for the IP core in question (this is often used for hard blocks like PLLs and transceivers as thay don't have RTL code), or one of two other options. The old flow for encrypted cores was to generate a non-synthesisable netlist description for the IP block, but this is largely being replaced by IEEE encryption. For IEEE encrypted cores, Altera releases a version of the code that encrypts the code with an Altera specific key, and separate versions of the code that are encrypted with each simulation vendor's encryption key. Quartus can only decrypt and synthesise the Altera encrypted file, and each simulator tool can only decrypt the version of the code encrypted for it.