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So, what does the "simulation" folder bring to the party ?
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In my experience, absolutely nothing.
When I started using Qsys and SOPC Builder I found it very annoying that the tool would *copy* code, rather than simply providing a link to the source file. Copying the file makes it a pain, since any edits to the Avalon-MM slave or whatever you are working on, do not get reflected in the synthesis unless you re-run "Generate" (a pointless step).
I recently found the "work-around" for custom logic; in the _hw.tcl file, rather than add your files, add a .qip file that points to your source. You can setup components.ipx to make sure Quartus knows the paths to all your custom source.
Bottom line is that I don't think the Qsys files generation was well thought out, i.e., there are many typical use-cases that were not considered.
For example, if you use VHDL and put your code into various VHDL libraries, then Qsys _hw.tcl does not have any support for describing the library in which to compile code, or which library include statements to include in the generated wrapper file. The "solution" is to use the Tcl "generate" callback to construct your own top-level file, and to construct your own .qip files with the appropriate library directives.
Cheers,
Dave
Honored Contributor
