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Altera_Forum's avatar
Altera_Forum
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12 years ago

Why don't we simulate the synthesis code ?

Hello, I have a long standing methodological question about the IP generation tools from Altera. They seem to all generate 2 sets of VHDL/Verilog code: one for synthesis, one for simulation. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Sure, for example:

I want to produce an avalonMM interconnect system out of the Qsys tool. Once generated, and only asking for the (VHDL) simulation models (ie. not the testbenches) I get 2 sub-folders "simulation" and "synthesis".

What is the difference of the code lying under the "simulation" folder and under the "synthesis" one ?