why do I see packets on the user side of the 25G MAC when no fiber is plugged in?

HI,

I don't see the st_tx_x ports in the signal tap. Signal tap result is only showing st_rx_x port.

Anyway, you can check for 25G Ethernet user guide doc for internal loopback register control detail.

• For instance, check out page 66 of user guide, table 21 if you are using Arria 10 FPGA else you can search for respective FPGA 25G user guide
• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_25gbe.pdf

I can help you better if you shared with me Ethernet connection setup on your board system.

Like wise, pls try out 25G Ethernet example design and also verify FPGA power, clock and reset operation is handle correctly and within spec. (as I suggested earlier)

Thanks.

Regards,

dlim