Forum Discussion
Deshi_Intel
Regular Contributor
6 years agoHi Mark,
Can you share with me your Ethernet connection setup diagram on how everything is connected to FPGA 25G Ethernet IP ?
One suggestion for you is can you try out 25G Ethernet example design to see if you are able to duplicate issue ? This will helps to ensure you have all the correct setting.
Other common debug practice will be to ensure FPGA power, clock and reset operation is handle correctly and within spec.
Thanks.
Regards,
dlim