TGao
Occasional Contributor
Occasional ContributorWhy can PLL + LPDDR2 compile success in Quartus 17.1, but fail in 13.1?
Device：5CEBA4U15I7N The reference clk of lpddr2 is connected to the output of pll, the project can compile success in 17.1 but failed in 13.1. Error: Failed to find PLL reference clock.
