why atx pll output clock should be half of data rate?

When using serial protocols such as Serdes / PCIe, etc, the output data rate is achieved by using both edges of the clock. This is called Double-Data Rate (DDR) . In this scenario , to achieve the high data rate we only need to use the clock with half of the data rate. When the data is output at both edges (rising and falling) of the half rate clock, you will get the full data rate of the protocol.