Why address space bytes allocated by QSYS does not match the SPI IP core ?

I try putting an Avalon MM Pipeline Bridge between master port and the SPI IP , The parameter settings of Avalon MM Pipeline Bridge are as follows Figure 4. In the case,the number of SPI IP bytes that Qsys automatically allocates is 32 bytes(see Figure 5).

At this time, the slave port of Avalon MM Pipeline Bridge connected to the master port of bus bridge module component(External_bus_to_Avalon.v) (see Figure 6), and the master port of Avalon MM Pipeline Bridge connected to all slave port of other components(see Figure 7) (The slave port of other components connected to the master port of bus bridge module component original).

I want to confirm this method right.

Looking forward to your answer, thank you!