Forum Discussion
Is your custom master properly acknowledging waitrequest? When waitrequest to the master is high, the master must continue asserting the control signals, like write, until the clock edge after waitrequest is deasserted by the interconnect. This may be why you're seeing the correct behavior when you hold the write. When you remove the other master, no arbitration is needed so a single pulse write is working, but you should still be coding waitrequest correctly.
Thanks a lot for the inputs. The issue is exactly because the master is not acknowledging the waitrequest. We didn't acknowledge waitrequest earlier because we assumed the waitrequest master sees will be the thing which slave sends, And the custom slave's(FIFO) waitrequest signal is hardcoded to zero. The above statement seems to be true only if there is a single master connected to slave. But with multiple masters, interconnect generates it's own waitrequest(Being high) even though at no point of time more than one master are trying to access slave simultaneously.