While writing from Multiple Avalon Master to an Avalon slave, Write from custom Avalon Master is not generating write signal in slave side.

Is your custom master properly acknowledging waitrequest? When waitrequest to the master is high, the master must continue asserting the control signals, like write, until the clock edge after waitrequest is deasserted by the interconnect. This may be why you're seeing the correct behavior when you hold the write. When you remove the other master, no arbitration is needed so a single pulse write is working, but you should still be coding waitrequest correctly.