Forum Discussion

CTham1's avatar
CTham1
Icon for New Contributor rankNew Contributor
7 years ago
Solved

While writing from Multiple Avalon Master to an Avalon slave, Write from custom Avalon Master is not generating write signal in slave side.

Hi All, I'm using Cyclone V development kit, I have a design with two avalon masters (JTAG Master and custom master) connected to a custom Avalon slave interface through qsys. The issue is when the...
  • sstrell's avatar
    sstrell
    7 years ago

    Is your custom master properly acknowledging waitrequest? When waitrequest to the master is high, the master must continue asserting the control signals, like write, until the clock edge after waitrequest is deasserted by the interconnect. This may be why you're seeing the correct behavior when you hold the write. When you remove the other master, no arbitration is needed so a single pulse write is working, but you should still be coding waitrequest correctly.

KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
7 years ago
Can you try to simulate your design in Modelsim? There are few type of fifo in the platform designer, which specific fifo that you were using? Can you attached your *.qsys file here?
  • CTham1's avatar
    CTham1
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi,

    We have few more observations, When we increase the pulse width of write signal to two clock period in the custom master then we are able to see the slave is getting a single clock write pulse.

    One more observation is even the other master (JTAG Master) is creating a write signal for two clock pulse when we perform a single write operation, Is this what is expected in the custom master as well? Do we have any documentation to explain that?

    Note:

    The clock and reset of both master and slave is same.

    Also when only custom master and slave are connected (No other master to slave) then even a single clock pulse of write from master is able to generate a single clock write pulse in slave.

    Any help in this regard will be highly appreciated. Thanks in advance:)

    KTan9,

    Thanks for the reply,

    Simulating things will be difficult as all these things are in qsys. We are using the FIFO IP of Altera with a wrapper around it.