Which FPGA IP can be used FREE in production with the Quartus LITE dev. sw?

I tested a bit in Quartus Prime Light (20.1.1) for a MAX10 (10M50DA type), and these are some findings.

- It seems it's the more elaborate IPs that needs paid licenses (as has been said), so PLLs, use of ADC in MAX10, etc. are free

- You can disable use og Evaluation licenses:

Assignments > Settings > Compilation Process Settings > More Settings > Intel FPGA IP Evaluation Mode: Disable

- In the Compilation Report you can check (examples when disabled):

- Assembler > Encrypted IP Cores Summary (Gives for example: Nios II Embedded...: Unlicensed; Signal Tap: Licensed)

- Assembler > Messages (gives for example)

- 115003 Can't generate programming files ... not valid license for following IP core(s)
115005 Unlicensed IP: "Nios II Embedded Processor Encrypted output..."
115004 Unlicensed encrypted design file: "c:/....../altera_nios_gen2_rtl_module.sv"

- When Evaluation mode is Enabled, you get the programming file <name>_time_limited.sof (as Frank said earlier).

- You can also check in the Compilation Report

- Analysis & Synthesis > IP Cores Summary, the Licence Type column
For example: Signal Tap: Licensed; no licence needed (it seems): N/A, Nios II Embedded...: OpenCore (not free)

(Nios II is btw outdated, Nios V should be used for new designs, but it needs a paid license as well.)

So, I'm a bit more optimistic, seems that much of the simpler IP in Platform Designer in Quartus can be used.