whether txdatavalid signal should be drivien by mac as 1 or 0 in pcie serdes architecture mode.

Hi Srilakshmi,

Great to hear from you again. It seems like we are looking at the same documentation.

As defined, the TxDataValid signal is to allow the MAC to instruct PHY to ignore the data interface for one clock cycle. Furthermore, the MAC is required to assert TxDataValid (set it to 1) at all times when the PHY is in a mode that does not require the signal.

From the documentation, there are a few situations in which we need to make use of the TxDataValid signal. For instance:

1.Electrical Idle

The MAC should have TxDataValid asserted whenever TxElecIdle toggles. This is because the TxDataValid signal is used as a qualifier for sampling TxElecIdle.

2.128b/130b Encoding and Block Synchronization

For 128b/130b encoding, the MAC must use the TxDataValid signal periodically to allow the PHY to transmit the built-up backlog of data.

To illustrate, let TxData bus = 16-bit wide, PCLK = 500 MHz. Then, for every 8 blocks, the MAC must deassert the TxDataValid signal for one PCLK. This is to allow PHY to transmit the 16-bit backlog of built-up data. The MAC must deassert the TxDataValid signal for one clock cycle immediately after the end of the Nth transmitted block. This means that the TxDataValid must be deasserted for one clock, exactly every N blocks. N can be calculated as follows:

N = 4 for an 8-bit-wide interface if the PIPE interface is operating at 8 GT/s;

N = 8 for a 16-bit-wide interface if the PIPE interface is operating at 16 GT/s.

You may refer to Section 8.19 and Section 8.27 in the documentation for (1) and (2), respectively, for a thorough understanding. I hope this addresses your question well.

Thanks.

Best Regards,

VenTing_Intel

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