lv0001New Contributor6 years agoWhen i try to simulate a PCIE example design the simulation time is very large. How can it be optimized to reduce the simulation time
KennyT_alteraSuper Contributor6 years agoYou can refer to https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/model-sim.html, you may have to contact mentor for the purchase
Recent DiscussionsSysID TimestampCyclone 10 GX Transceiver Power-Up Calibration Time (~353 ms) Analysis RequestAVST FIFO and AVST Demultiplexer IP Simulation BehaviorUser controlled burst refreshF-tile ethernet hard ip in agilex7