New Contributor
Frequent ContributorI am assuming you are using the UniPHY EMIF in Cyclone V /Arria V/Stratix V device right?
After you generate the example design, you need to use quartus open the generate_sim_example_design.qpf under simulation folder. Then go to tools, tcl scrips... and select generate_sim_verilog(VHDL)_example_design.tcl and run. After the tcl executed, you can see the memory model generate under the submodules folder with name - alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv
When using the example design, actually you do not need to worry about where the memory model located. You can just run the simulation script based on the simulation that you using.
Refer to this chapter to run the example design simulation - 8.2.5. Simulating the Example Design
New Contributoryes, we are using uniPHY EMIF Arria V device only. whether memory model of example design can be used for our design...how can we use and where can we pick.....does it support micron memory model?we are planning to use micron memory..if not which memory can be supported?
