Forum Discussion
Altera_Forum
Honored Contributor
16 years agoif it is just that simple you could write
module MyPower ( clk , In_N , Out_P ); input clk; input [ 3:0] In_N; output [15:0] Out_P; reg [15:0] Out_P; always @ ( posedge clk ) case ( In_N ) 4'd0 : Out_P <= 16'd1; 4'd1 : Out_P <= 16'd2; 4'd2 : Out_P <= 16'd4; 4'd3 : Out_P <= 16'd8; 4'd4 : Out_P <= 16'd16; 4'd5 : Out_P <= 16'd32; 4'd6 : Out_P <= 16'd64; 4'd7 : Out_P <= 16'd128; 4'd8 : Out_P <= 16'd256; 4'd9 : Out_P <= 16'd512; 4'd10 : Out_P <= 16'd1024; 4'd11 : Out_P <= 16'd2048; 4'd12 : Out_P <= 16'd4096; 4'd13 : Out_P <= 16'd8192; 4'd14 : Out_P <= 16'd16384; 4'd15 : Out_P <= 16'd32768; endcase endmodule but you could try to implement some kind of shift functionality