What is the best way for a NIOS II to communicate with the DDR3 SDRAM on the Cyclone 10 GX dev kit?

The design is based on the example design from the EMIF IP Parameter Editor provided with the Cyclone 10 GX dev kit which comes with a width of 320 and also a burst interface, see attached image. I assume the 320 width comes because of the hardware requirements of DDR3. I can deal with the address span with the Address Span expander IP, but I cannot just hookup the NIOS to the example design because of the bursting and the difference in data width. I have tried looking for example designs for the Cyclone 10 GX with the NIOS connected to DDR3, but to no success. It's looking like I am going to need build a custom instruction module to get them to communicate.