Skip to contentBrand Logo
Forums
BlogKnowledge BaseAltera.com
RegisterSign In
  1. Altera Community
  2. Forums
  3. IP & Transceiver

Forum Discussion

vRaju5's avatar
vRaju5
Icon for New Contributor rankNew Contributor
6 years ago

what is an equivalent IODELAY2 Primitive of Xilinx-spartan6 in quartus prime ?

https://www.xilinx.com/support/documentation/user_guides/ug381.pdf

page no.70 to 75.

1 Reply

  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hi,

    I am kindly requesting to use Programmable IOE Delay for Intel FPGA devices.

    For your reference page no:140. of the below document.

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

Recent Discussions

  • TSUGI's avatar
    What Bank Mode of LPDDR5 does Agilex 5 support?
    3 days ago
    TSUGI
  • TSUGI's avatar
    What is source clock of rx_core_clkout of Serial Lite IV IP
    4 days ago
    TSUGI
  • drbarryh's avatar
    Confusion for TX Clock direction for Triple Speed 1G Ethernet IP?
    4 days ago
    drbarryh
  • wangduoyu's avatar
    Agilex 5: Connecting multiple AXI Masters to DDR without explicit Interconnect IP
    4 days ago
    wangduoyu
  • MichaelL's avatar
    Behavior of 10 GX Avalon-MM Interface for PCI Express* IP Core when byteenable=16'h0000
    6 days ago
    MichaelL
Contact Us
Altera YoutubeAltera YoutubeAltera Twitter
  • Company Overview
  • Newsroom
  • Our Leaders
  • Careers
Subscribe to Altera Newsletter

© Altera Corporation | Terms of Use | Privacy Policy | Cookies | Trademarks | PSIRT

Altera Logo