what condition to get JESD204B serial output pin toggling? (it is urgent)

Hie, My apologies for the delayed first response. I has a few JESD204B cases and missed this case. To enable the JESD204B IP's Tx out (serial out) to toggle, this are the requirement: i. correct frequency free running reference clock is available to PLL ii. phy and base IP is out of reset iii. calibration or system clock is available to IP iv. Rx issues sync request (sync_n) is asserted. This will transition the Tx into CGS (code group synchronization) state which will cause Tx to transmit idle K28.5 characters which will cause Tx out to toggle. Please check if above requirements are met to generate output signal in serial bus. Regards, Nathan