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BIdro's avatar
BIdro
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

What are the important settings for SDI-SD standard video communication? I use the IP-SDI-II up to SDI-HD and it works properly, but it does not work with SDI-SD. How can I generate a correct differential signal for SDI-SD standard?

The IP-SDI-II supports SDI-SD standard but It uses a 148.5 MHz clock signal as reference. It oversamples the data because the correct frequency should be 13.5 MHz. I use an interface component that e...
BIdro's avatar
BIdro
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi Cpchan,

I used the fifo and the image is better but there are incorrect lines in each frame.

I saw with Signal Tap tool that, after some time, TX lost 1 read from fifo, so Luma and Croma are exchanged and I suppose that is the error.

My board has not an external VCXO to clean up the recovered clock before feeding into TX as XCVR refclk.

Is it wrong, if I use a internal PLL to generate tx-XCVR?

A VCXO has not a clock reference input but it has a voltage control input. How can I set the correct frequency for TX?

Can VCXO be connected to an internal PLL of mt FPGA (CYCLONE V GT)?

thanks

Bryan