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BIdro's avatar
BIdro
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

What are the important settings for SDI-SD standard video communication? I use the IP-SDI-II up to SDI-HD and it works properly, but it does not work with SDI-SD. How can I generate a correct differential signal for SDI-SD standard?

The IP-SDI-II supports SDI-SD standard but It uses a 148.5 MHz clock signal as reference. It oversamples the data because the correct frequency should be 13.5 MHz. I use an interface component that e...
BIdro's avatar
BIdro
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi Cpchan,

I'm using Quartus Prime 18.1 Standard Edition and the FPGA is Cyclone V - 5CGTFD5C5F2717.

I create a component with the wizard tool and I set it up to SD-SDI transmitter only.

I create an other component as SDI-SD receiver and I can see TRS,EAV, vertical and horizontal blanking signals from an external SDI-SD pattern generator with Signal Tap tool.

I connected TX_CLKOUT to TX_PCLK.

TX_CORECLK and XCVR_REFCLK are 148.5 MHz signals and they are generated using a PLL that has RX_CLKOUT (148.5 MHz) signal as reference frequency.

TX_DATAIN_VALID is connected to TX_DATAOUT_VALID that is sampled with TX_PCLK signal.

Is the TX set up properly?

thanks

Bryan