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SMcCa9's avatar
SMcCa9
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7 years ago

What are the Avalon-MM addresses used for the JESD204 IP Core in dynamic reconfiguration for modifying the LMFSK and data rate parameters?

Hello, I am working on a project utilizing the JESD204B IP offered by Intel on an Arria V GZ FPGA using Quartus II Standard 14.0. Part of the project requires dynamic reconfiguration of the JESD204B...
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago
Hie Samual, My apologies for the delayed first response. I got your case mixed up with another JESD forum question; hence I missed providing an update. Firstly, for Arrua V GZ FPGA when using JESD 204B IP, you do not need to manually write to the registers to perform reconfiguration through AVMM. When a Trasceiver Reconfiguration Phy IP is connected to the JESD IP, a MIF file (configuration file) will be generated for every configuration. MIF file has all the register values required to perform reconfiguration. This details are explained in our JESD IP user guide (Section 1.6.4; Pg 54) below: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-design-ex-jesd204b.pdf The steps to perform reconfiguration through MIF file is also described in the Transceiver Phy User Guide: (Pg 17-43 to Pg17-46) https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf Please let me know if you need additional information on performing the reconfiguration for JESD204B IP. Regards, Nathan
  • SMcCa9's avatar
    SMcCa9
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    7 years ago

    Hi Nathan,

    Thank you for your response. I had gone through those PDFs before, but missed the details I was looking for.

    I will look through the referenced materials and let you know if I have any follow up questions.

    Best,

    Samual