Hi,
The DDR3 IP configuration and on board SDRAM configuration needs to match else DDR3 will failed calibration.
Let me reiterate again - the supported ECC option in DDR3 IP is either 16, 24, 40 or 72.
- You cannot key in any other value when ECC option is on
- There is no 64 bits option with ECC on
- ECC bits will always be the last 8 bits of your DQ data bus, can't be in the middle of DQ bus
The only option that will works for your setup is as below
- 72 bits configuration = 64 DQ bits + 8 ECC bit
- DDR3 IP will generate 72 bits DQ bus connection
- On board SDRAM also needs to have 72 bits to match and connect to FPGA DDR3 72 bits
After that, if your user application just needs to use 45 bits then you need to add extra processing design to manually encode/decode padding of the rest of unused DQ bit to either 0 or 1. This is due to every DDR3 burst will send 72 bit.
- Typically user application can use Avalon bus byteenable feature to mask unused DQ data bit but that's control in byte form (8 bits per group)
- There is no control feature that can support unique 45 bits grouping. You need to create your own processing design
Thanks.
Regards,
dlim
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