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sbala31's avatar
sbala31
Icon for New Contributor rankNew Contributor
6 years ago

We need example design of DDR3_lower with ECC option for Arria-V 5AGXFB3H6F40C6 device EVM module

we tried to generate ddr3_lower with ECC option . we had doubts on whether separate data pin will be allocated for ECC or not. to confirm that we need example file.
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Yes, I can see you configured DQ = 56bits. DDR3 IP prompt error because this is invalid configuration setting

but I think you didn't get my point.

What I am trying to tell you is "45 bit+8 bit ECC" is invalid configuration because "45 bits DQ" is not a valid configuration at all.

  • There is no option that you can set in DDR3 IP to accept either "45 bit+8 bit ECC" or "just 45 bits DQ without ECC".
  • It doesn't make sense to support 45 bit DQ as I explained in previous post. There is no DDR3 SDRAM chip that support 45 bit configuration

The error message already explained the supported ECC option which is 16, 24, 40, 72

  • 16 configuration = 8 DQ bit + 8 ECC bit
  • 24 configuration = 16 DQ bit + 8 ECC bit
  • 40 configuration = 32 DQ bit + 8 ECC bit
  • 72 configuration = 64 DQ bits + 8 ECC bit

I hope I clear your doubt now

Thanks.

Regards,

dlim

  • sbala31's avatar
    sbala31
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi ,

    Yes, I understood that we cant use 45 + 8 bit ecc. But I am having doubt in how to map this 45 bit data + 8 bit ECC. I need to store 45 bits data in memory . if ecc enabled , 8 bit extra bits will be allocated. For this requirement, 64 bit controller only can be used. is this correct?

    In 64 DQ pins, 0 to 44(data) and 56 to 63(ECC) Pins will be used. remaining DQ pins will be dummy data.

    To store that data, 4x16 bit DDR memory going to be used. first 3 DDR memory will be used to store data.( refer below diagram for connection)

    Can we connect last 8 DQ pins to first 8 bits of chip4.