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sbala31's avatar
sbala31
Icon for New Contributor rankNew Contributor
6 years ago

We need example design of DDR3_lower with ECC option for Arria-V 5AGXFB3H6F40C6 device EVM module

we tried to generate ddr3_lower with ECC option . we had doubts on whether separate data pin will be allocated for ECC or not. to confirm that we need example file.
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

As the DDR3 IP error message explained, 45 bits is not a valid configuration for DDR3.

DDR3 SDRAM chip typically comes in either x4, x8 or x16 DQ data bits width. So, the valid configuration will always be multiply of 4, 8, or 16.

  • For instance, to build x32 DQ configuration
  • User can connect to 8 "x4 SDRAM" chip
  • Or User can connect to 4 "x8 SDRAM" chip
  • Or User can connect to 2 "x16 SDRAM" chip

I never encounter physical DDR3 SDRAM chip that can support 45 bits. That's why you see the error message as this is invalid configuration or none standard configuration

Thanks.

Regards,

dlim

sbala31's avatar
sbala31
Icon for New Contributor rankNew Contributor
6 years ago

Thanks for the reply. We tried with 56 bit controller only not 45 bit(Please check the attached screenshot). our doubt is "which interface datawidth(48,56,64) should be selected for our required data 45 bit+8 bit ECC?".