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sbala31's avatar
sbala31
Icon for New Contributor rankNew Contributor
6 years ago

We need example design of DDR3_lower with ECC option for Arria-V 5AGXFB3H6F40C6 device EVM module

we tried to generate ddr3_lower with ECC option . we had doubts on whether separate data pin will be allocated for ECC or not. to confirm that we need example file.
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

There is no special example design for ECC enablement but I can explain how DDR3 IP manage ECC option.

In DDR3 IP,

  • If user set DQ = 40 with controller ECC option ON
    • DQ [39:32] will be the ECC bit
  • If user set DQ = 72 with controller ECC option ON
    • DQ [71:64] will be the ECC bit

Meaning if ECC option is turned on, the last 8 DQ bit will be the ECC bit.

Thanks.

Regards,

dlim

sbala31's avatar
sbala31
Icon for New Contributor rankNew Contributor
6 years ago

Thanks for your reply. For our confirmation , we need to use 45bit datawidth + 8 bit ECC . so we need to generate 64 bit ddr3 controller with ECC. Please confirm . If we try to generate 56bit DDR3 controller with ECC The error message which is shown in tool window is attached here. PFA.