Hi,
Just to update you on the latest finding. For your information, I have managed to perform simulation with IP (mimic your configuration) generated example design and there is no issue with the simulation after applying the fix that you mentioned in the previous note for test_program.sv. Input data and output data looks normal in the example simulation.
As I further look into your design simulation and cross check with the example simulation, I observe that in your design, the first batch of in_data to CIC IP has invalid bit[17] = StX as shown in the invalid first batch of input data.png. I suspect that due to this invalid first batch of data, it leads to corrupted data for the subsequent output. I have then tested forcing the in_data to a dummy data in your top level file and rerun the simulation. After feeding valid data, I am able to see valid output at the CIC IP in the simulation as shown in the after_fix_first_batch_data_ok.png.
It would be great if you could help to look into your data source to the CIC in_data to see what might have cause the first batch of source data to be invalid.
Note that I am unable upload the screenshot to the case, probably due to server issue. Thus, I am sending them to you through email.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Occasional Contributor
