Occasional Contributor
Frequent ContributorHi, Xiaoqiang
Warning (15055): PLL "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_pll0:pll0|altpll:upll_memphy|altpll_i0j3:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
Info (15024): Input port INCLK[0] of node "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_pll0:pll0|altpll:upll_memphy|altpll_i0j3:auto_generated|pll1" is driven by clock_pll:clock_pll_0|clockpll:clk|altpll:altpll_component|clockpll_altpll:auto_generated|wire_pll1_clk[1]~clkctrl which is OUTCLK output port of Clock control block type node clock_pll:clock_pll_0|clockpll:clk|altpll:altpll_component|clockpll_altpll:auto_generated|wire_pll1_clk[1]~clkctrl
Warning (15058): PLL "nios_mem_if_ddr2_emif_0:mem_if_ddr2_emif_0|nios_mem_if_ddr2_emif_0_pll0:pll0|altpll:upll_memphy|altpll_i0j3:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[1] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins
You may want to check if INCLK[0] is a dedicated clock input pin.
Thanks.
Eric
