Occasional Contributor
Occasional Contributorone more:
PLL clock mem_if_ddr2_emif_0|pll0|upll_memphy|auto_generated|pll1|clk[0] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL, and not go through a global clock network. Timing analyses may not be valid.
Regular ContributorHi,
You may refer to the KDB: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd12102013_751.html
It is recommended that you use a dedicated clock input pin that is directly routed to the memory controller reference clock input.
Thanks
Best regards,
KhaiY
Regular ContributorHi,
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Best regards,
KhaiY
