Waitrequest ALTMEMPHY DDR2 Controller

This is probably one of the most common mistakes I have seen others make..... including myself from time to time. Unfortunately it's more difficult to spot this mistake in Qsys. In SOPC Builder you would see a bunch of messages about "clock_0", "clock_1", etc... fly by the screen when the system is generating which was a hint if you were running into this.

In Qsys you can setup the type of clock crossing technique used, for example you can force it to instantiate clock crossing FIFOs instead of the handshake ones that were generated into your system. The handshake clock crossing adapters move only one word of data at a time which is why you were seeing that efficiency problem. The FIFO clock crossing adapters use dual clock FIFOs to move the data between domains and they can handle multiple transactions in flight. This option is only available in Qsys, to get the same behavior in SOPC Builder you would have to use the clock crossing bridge which implements practically the same thing.