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Altera_Forum
Honored Contributor
Honored ContributorWaitrequest ALTMEMPHY DDR2 Controller
Hi, I have a problem with the ALTMEMPHY DDR2 Controller. I try to build a FIFO using the external DDR2 ram. In principle, the FIFO works but I do not achieve the required speed. With a (own wri...
Altera_ForumHonored Contributor
Honored ContributorYep it's clock crossing causing this. That DDR_FIFO_0 component is on the "pll_c0" clock domain meanwhile the SDRAM slave port that it connects to is on the "DDR_sysclk" domain. Switch the DDR_FIFO_0 clock domain to DDR_sysclk and you should not get a clock crossing adapter between the two components and you won't see the waitrequest throttle your master much.
