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Altera_Forum
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13 years ago

Waitrequest ALTMEMPHY DDR2 Controller

Hi, I have a problem with the ALTMEMPHY DDR2 Controller. I try to build a FIFO using the external DDR2 ram. In principle, the FIFO works but I do not achieve the required speed. With a (own wri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi BadOmen

Many thanks for your answer. So the first thing I did was to remove the beginbursttransfer signal but nothing changed. Then I checked the parameters of the DDR2 Controller and the clocking. Unfortunately, I can’t find an error. There are some screenshots in the attachment.

Some more information that may be important:

- Using Quartus II version 12

- FPGA: EP4CE75F23C8N

- DDR2 RAM: W971GG6JB-25

- RAM is connected to Bank7 and Bank8 (thus on the top I/O banks, right?)

Thanks a lot and best regards

Christian