Waitrequest ALTMEMPHY DDR2 Controller

Take some screenshots of your memory parameterization. Are you making sure your master and the local interface of the SDRAM controller are on the same clock domain? (called sysclk... or something similar from the SDRAM controller PLL)

Also I don't recommend ever implementing beginbursttransfer. That's a signal that is not necessary and it's also difficult to time since it doesn't heed waitrequest. As far as I can tell your master is doing nothing wrong so I suspect there is a clock crossing between it and the memory. The asynchronous handshake clock crosser that automatically gets inserted can only let one transfer through at a time while the data changes clock domains which is what it looks like in your STPII capture.