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Altera_Forum
Honored Contributor
Honored ContributorWaitrequest ALTMEMPHY DDR2 Controller
Hi, I have a problem with the ALTMEMPHY DDR2 Controller. I try to build a FIFO using the external DDR2 ram. In principle, the FIFO works but I do not achieve the required speed. With a (own wri...
Altera_ForumHonored Contributor
Honored ContributorTake some screenshots of your memory parameterization. Are you making sure your master and the local interface of the SDRAM controller are on the same clock domain? (called sysclk... or something similar from the SDRAM controller PLL)
Also I don't recommend ever implementing beginbursttransfer. That's a signal that is not necessary and it's also difficult to time since it doesn't heed waitrequest. As far as I can tell your master is doing nothing wrong so I suspect there is a clock crossing between it and the memory. The asynchronous handshake clock crosser that automatically gets inserted can only let one transfer through at a time while the data changes clock domains which is what it looks like in your STPII capture.
