VVP RAM Clk

Hello,

  I am using VVP Pixels In Parallel converter Lite Mode, convert from parallel pixels from 4 to 2.

Configurations see below.

All the connections are fine and no error messages on Platform Designer.

But failed to pass synthesis for errors like, clock connection..

  How can I debug this issue?

The project is running on Quartus Pro 25.3.0.

Thank you.